Novel simulation of deep-submicron MOSFET circuits

Author

Bruma, Serban ; Otten, Ralph H J M

Author_Institution

Fac. of Electr. Eng., Delft Univ. of Technol., Netherlands

fYear

1997

fDate

12-15 Oct 1997

Firstpage

62

Lastpage

67

Abstract

The effects of scaling down the MOSFET dimensions to the deep-submicron range lead to operating regions that may be modeled by locally linear equations. The piecewise linear simulator seems to be the obvious choice. Certain requirements must be satisfied by a PL simulator for the successful manipulation of the proposed MOSFET model. Simulation results demonstrate the efficiency in simulating large deep-submicron MOSFET circuits. Several levels of hierarchy can be simulated due to the uniform PL modeling technique

Keywords

MOSFET circuits; circuit CAD; circuit analysis computing; piecewise-linear techniques; MOSFET circuits; MOSFET model; PL simulator; deep-submicron; piecewise linear simulator; CMOS technology; Circuit simulation; Energy consumption; Integrated circuit interconnections; Integrated circuit technology; MOSFET circuits; Piecewise linear techniques; Semiconductor device modeling; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628850

Filename

628850