Delay Reduction Using Simulated Annealing

The MOST program chooses appropriate sizes for transistors in a VLSI schematic to meet specified delay criteria. A simulated annealing algorithm is used in conjunction with a timing analyzer, both written in Prolog. A screening function takes advantage of the symbolic equations provided by the timing analyzer to reject clearly inappropriate choices, so full timing analysis is performed less frequently. Despite running in an interpreted Prolog, performance gains of over 50% versus an unsized circuit can be attained in less than 10 cpu minutes.