Length scaling of hetero-gate dielectric SOI PNPN TFET

The silicon device technology faces problem when devices scale down to nanometer dimensions. Many challenges occur such as SCEs like drain induced barrier narrowing (DIBN), reduced I_on/I_off ratio, which may limit the operation. The goal of this paper is to present and an4275391alyze the SOI PNPN TFET and its properties. Here heterogate dielectric SOI PNPN TFET is used to reduce the ambipolar current at the drain side and to increase the tunneling current at the source side compare to conventional TFET. This device has the potential of improved I_on/I_off, low subthreshold swing, low on state resistance and, negligible DIBN as compared to conventional TFET. This device uses a gate controlled p⁺-n interband tunneling junction at the source and pocket where the n pocket is fully depleted. Moreover, the kink effect is also virtually removed considering optimized silicon layer thickness.