DocumentCode :
3156196
Title :
Global Forced Hierarchical Router
Author :
Kessenich, John ; Jackoway, Gary
Author_Institution :
Hewlett-Packard Company
fYear :
1986
fDate :
29-2 June 1986
Firstpage :
798
Lastpage :
802
Abstract :
The Global Forced Hierarchical Router routes a printed circuit board first using a coarse grid to globally approximate a routing solution, and then using a fine grid to complete each coarse cell sequentially. The global stage assigns net crossings to each coarse cell border without specifying the exact location of crossing or layer number. The sequential stage takes each coarse cell and completely routes the cell. All that resides in memory is the coarse grid, a fine grid large enough to route one coarse cell, and the list of segments created by the sequential stage. The global stage routes quickly because it uses a coarse grid; the sequential stage routes quickly because its cells are small and therefore simple.
Keywords :
Design automation; Integrated circuit interconnections; Pins; Printed circuits; Prototypes; Routing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation, 1986. 23rd Conference on
ISSN :
0738-100X
Print_ISBN :
0-8186-0702-5
Type :
conf
DOI :
10.1109/DAC.1986.1586180
Filename :
1586180
Link To Document :
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