MipsCoreDuo: A multifunction dual-core processor

Author

Wakasugi, Yuhta ; Fujieda, Naoki ; Takamaeda, Shinya ; Kise, Kenji

Author_Institution

Grad. Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Tokyo, Japan

fYear

2009

fDate

7-9 Jan. 2009

Firstpage

587

Lastpage

590

Abstract

In this paper, we describe the architecture of MipsCoreDuo, a microprocessor which is designed for LSI Design Contest in Okinawa 2009. MipsCoreDuo is a multifunction dual-core processor that has four attractive execution modes. It achieves high-parallel performance, high-sequential performance or high-dependability with single design. We implemented it in Verilog-HDL targeting an FPGA, and evaluated its performance. As a result,MipsCoreDuo uses 5,117 LUTs and achieves 71.8 MHz frequency. And Striping mode, which is one of the execution modes that uses two cores to boost a single-thread program, achieves 8-17% better performance on sequential application than conventional dual-core design.

Keywords

field programmable gate arrays; hardware description languages; microprocessor chips; multiprocessing systems; FPGA; MipsCoreDuo architecture; Striping execution mode; Verilog HDL implementation; dual-core processor; field programmable gate array; frequency 71.8 MHz; multifunction dual-core processor; Acceleration; Large scale integration; Microprocessors; Multicore processing; Out of order; Signal design; Signal processing; Switches; Transistors; Yarn;

fLanguage

English

Publisher

ieee

Conference_Titel

Intelligent Signal Processing and Communication Systems, 2009. ISPACS 2009. International Symposium on

Conference_Location

Kanazawa

Print_ISBN

978-1-4244-5015-2

Electronic_ISBN

978-1-4244-5016-9

Type

conf

DOI

10.1109/ISPACS.2009.5383772

Filename

5383772