Low power multiplexer decomposition

The advent of portable digital devices such as lap-top personal computers has made low power circuit design an increasingly important research area. Recently, low power decomposition for simple logic gates such as AND and OR has been extensively researched. However, the problem of MUX decomposition to minimize power dissipation has not been addressed. In this paper, we study the problem of low power multiplexer (MUX) decomposition. MUX decomposition is the procedure of transforming an n-to-one MUX into an equivalent tree of two-to-one MUXes. We propose a formulation for the minimum power MUX decomposition problem based on the common CMOS pass transistor implementation of a MUX. Given the occurrence probabilities of the data signals and their on probabilities, we analyze the power dissipation of OUT MUX implementation and give a general method for computing the power dissipation of a MUX tree decomposition. We then present several algorithms which efficiently generate minimum power MUX decompositions. We demonstrate the effectiveness of our algorithms with experimental results.