Re-mapping for low power under tight timing constraints

Author

Vuillod, P. ; Benini, L. ; De Micheli, G.

Author_Institution

Comput. Syst. Lab., Stanford Univ., CA, USA

fYear

1997

fDate

18-20 Aug. 1997

Firstpage

287

Lastpage

292

Abstract

In this paper we propose a novel approach to synthesis for low power under tight timing constraints. Starting from a mapped netlist, we apply a powerful generalized matching algorithm based on Boolean relations that allows us to find reduced-power replacements for clusters of more than one cell. Our approach is robust and scales well with circuit size it has been tested on all largest examples of the MCNC91 benchmark suite. In average, power is reduced by more than 17% with no speed penalty compared to minimum delay implementations. Area is virtually unchanged.

Keywords

Boolean functions; CMOS logic circuits; circuit CAD; circuit optimisation; combinational circuits; logic CAD; timing; Boolean relations; CMOS circuits; cell clusters; generalized matching algorithm; logic synthesis; low power design; mapped netlist; power reduction; reduced-power replacements; timing constraints; Benchmark testing; CMOS logic circuits; Circuit synthesis; Circuit testing; Constraint optimization; Cost function; Engines; Permission; Robustness; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Low Power Electronics and Design, 1997. Proceedings., 1997 International Symposium on

Conference_Location

Monterey, CA, USA

Print_ISBN

0-89791-903-3

Type

conf

Filename

621300