Device and technology optimizations for low power design in deep sub-micron regime

This report, based on the most recent analytical and experimental studies of CMOS scaling and gate delay models, reexamines the fundamental design quantities such as driving current, I/sub dsat/, propagation delay, t/sub pd/, and switching energy, E, and investigates device optimization issues in deep sub-micron regime. Empirical I/sub dsat/ equations and device optimization guidelines with gate oxide, channel length and power supply scaling as well as interconnect loading are extracted.