Low power synthesis via transparent latches and observability don´t cares

We describe a synthesis technique for power optimization in combinational logic circuits. We remove unnecessary signal transitions in circuits by adding transparent latches. Observability don´t-care sets (ODCs) are used to find such transitions, places where latches are inserted, and conditions for disabling the latches. We propose an algorithm for adding transparent latches to reduce power dissipation in circuits, and a method for estimating the reduced power because of the latches. We also present experimental results to show the effectiveness of the technique on benchmark circuits