DocumentCode :
3156548
Title :
On-chip memory size configuration of SOC system based on real-time constraints
Author :
Wang, Bin ; Chen, ShuCong
Author_Institution :
Coll. of Commun. Eng., Hangzhou dianzi Univ., Hangzhou, China
fYear :
2011
fDate :
16-18 April 2011
Firstpage :
5094
Lastpage :
5096
Abstract :
In this paper, the relationship between scheduling cycle of embedded application and on-chip memory size configuration in SOC system is analyzed, and the method to select the optimal on-chip memory size under real-time constraints is present. The scheduling cycle and hardware cost is used to evaluate the approach. The result shows that the method has reduced scheduling cycle and hardware cost significantly.
Keywords :
memory architecture; processor scheduling; real-time systems; system-on-chip; SOC system; embedded application; hardware cost; optimal on-chip memory size configuration; real-time constraint; scheduling cycle; Conferences; Hardware; Random access memory; Real time systems; Schedules; Scheduling; System-on-a-chip; SOC; embedded system; memory configuration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Consumer Electronics, Communications and Networks (CECNet), 2011 International Conference on
Conference_Location :
XianNing
Print_ISBN :
978-1-61284-458-9
Type :
conf
DOI :
10.1109/CECNET.2011.5768652
Filename :
5768652
Link To Document :
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