Performance improvement of a genetic algorithm for floorplanning with parallel computing technology

Author

Foo, Han Yang ; Esbensen, Henrik ; Song, Jianjian ; Zhuang, Wenjun ; Kuh, Ernest S.

Author_Institution

Nat. Supercomput. Res. Center, Nat. Univ. of Singapore, Singapore

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1544

Abstract

This paper presents a parallel implementation of a genetic algorithm for floorplanning. It discusses the strategy and implementation and proposes a Multi-Selection-Multi-Evolution (MSME) parallelization scheme. The initial experimental results on a 12-node IBM SP2 scalable parallel computer have shown that the scheme is effective in improving performance of floorplanning over that of a serial implementation. The parallel version could obtain better results with more than 80% of probability and the improvements on chip area and maximum path delay could be more than 20% in the best cases

Keywords

circuit layout CAD; computational complexity; delays; genetic algorithms; integrated circuit layout; parallel algorithms; IBM SP2 scalable parallel computer; MSME parallelization scheme; floorplanning; genetic algorithm; multi-selection-multi-evolution parallelization; parallel computing technology; Clustering algorithms; Concurrent computing; Delay; Genetic algorithms; Iterative algorithms; Iterative methods; Parallel processing; Simulated annealing; Space exploration; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621423

Filename

621423