• DocumentCode
    315658
  • Title

    Design and implementation of a global router based on a new layout-driven timing model with three poles

  • Author

    Liu, Fang-Jou ; Lillis, John ; Cheng, Chung-Kuan

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
  • Volume
    3
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    1548
  • Abstract
    In this paper we present a new layout-driven timing model based on Asymptotic Waveform Evaluation (AWE) for improved timing analysis during routing. Our model enables the bottom-up computation of interconnect tree moments, and can be easily integrated with such a global router. Such an integration achieves incremental layout optimization, i.e., timing analysis and routing are tightly coupled, with feedback between them. This achieved incremental layout optimization, through our innovative timing model, is the main contribution of this work
  • Keywords
    VLSI; circuit layout CAD; circuit optimisation; delays; integrated circuit layout; network routing; timing; asymptotic waveform evaluation; bottom-up computation; global router; incremental layout optimization; interconnect tree moments; layout-driven timing model; timing analysis; Circuit analysis; Computer science; Delay effects; Delay estimation; Design engineering; Feedback; Integrated circuit interconnections; Performance analysis; Routing; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621424
  • Filename
    621424