Timing-driven pin assignment with improvement of cell placement in standard cell layout

In this paper, we propose a timing-driven pin assignment algorithm with improvement of cell placement in standard cell layout. The objective of the algorithm is to minimize the channel density as well as the total wire length by assigning nets to pins of cells under the given timing constraints. If the number of possible pin assignments for each cell is bounded by some constant r, then the proposed algorithm runs in linear time. In most practical cases, the value of r is relatively small, and thus the proposed algorithm is effective and efficient in reducing the chip area