An integrated synthesis system for speed-independent asynchronous circuits

In this paper, an integrated synthesis system is established to synthesize speed-independent asynchronous circuits directly from STGs with limited fanin basic gates. It combines asynchronous technology mapping and synthesis into an integrated one and thus can get the mapping solution for those whose mapping results can not be generated by previous separate mapping methods. In addition, the whole synthesis is carried out entirely on the STG level without generating the SGs and thereby preserve the problem size proportional to the number of signals. With the proposed method, STGs can be synthesized and hazard-free mapped circuits generated simultaneously in very low CPU time. Our method has been automated and applied to a large set of asynchronous benchmarks and industrial circuits