Aesop: A Tool for Automated Transistor Sizing

This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit\´s speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power. These algorithms are implemented in an interactive tool, Aesop. Aesop is a powerful and fast "what-if" tool that allows the designer to explore the space of designs having optimal transistor sizes. When compared to manual designs, the circuits produced by Aesop are typically faster or have substantially lower area and power consumption. Compared to untuned circuits, Aesop typically increases circuit speed by a factor of 2 to 4. Alternatively, power consumption and transistor area can be reduced by 25 -- 50% with no sacrifice in circuit speed. These improvements are computed interactively on a professional workstation for circuits containing thousands of transistors.