Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Author

Jou, Shyh-Jye ; Chuang, I-Yao

Author_Institution

Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

1808

Abstract

In this paper an efficient implementation of self-timed circuits whose hardware and control signals are significantly reduced is first proposed. By applying Globally Asynchronous Locally Synchronous (GALS) design techniques, the hardware overhead is further reduced. GALS and synchronous version of 8-bit fully pipelined array multipliers are implemented for comparisons. The results show that GALS version has smaller peak current, less power consumption under variable workload with small hardware overhead as compared to synchronous version

Keywords

adders; asynchronous circuits; logic arrays; multiplying circuits; pipeline arithmetic; timing; 8 bit; GALS; fully pipelined array multipliers; hardware overhead; low-power globally asynchronous locally synchronous design; peak current; power consumption; self-timed circuit technology; variable workload; Circuit synthesis; Clocks; Control systems; Delay; Energy consumption; Energy management; Hardware; Power system management; Protocols; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621497

Filename

621497