DocumentCode
315716
Title
Programmable design for memory sharing processor array
Author
Li, Dongju ; Kunjeda, H.
Author_Institution
Dept. of Electr. & Electron. Eng., Tokyo Inst. of Technol., Japan
Volume
3
fYear
1997
fDate
9-12 Jun 1997
Firstpage
2048
Abstract
Memory sharing processor array (MSPA) architecture has been proposed with advantages of high efficiency parallel processing, less data storage requirement, and high-cost performance. MSPA design methodology has been developed with regular structure and systematic procedure. In this paper, programmable MSPA is proposed. It embeds not only MSPA architecture, but design procedure into silicon chips so that various applications can be performed with high speed
Keywords
VLSI; digital signal processing chips; elemental semiconductors; integrated circuit design; parallel architectures; shared memory systems; silicon; DSP chips; VLSI; data storage requirement; high efficiency parallel processing; memory sharing processor array; regular structure; systematic design procedure; Application specific integrated circuits; Communication system control; Costs; Data engineering; Digital-to-frequency converters; Electronic mail; Memory; Parallel processing; Resource management; Signal generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.621558
Filename
621558
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