DocumentCode :
315724
Title :
Two´s complement high radix division
Author :
Bashagha, A.E. ; Ibrahim, M.K.
Author_Institution :
Dept. of Electron. & Electr. Eng., De Monfort Univ., Leicester, UK
Volume :
3
fYear :
1997
fDate :
9-12 Jun 1997
Firstpage :
2088
Abstract :
The existing two´s complement high radix division algorithms require a full wordlength addition per each possible value of the remainder. Therefore, a huge area is required to implement these algorithms. This paper presents a novel two´s complement radix-2k structure which replaces the full wordlength addition with a (k+2)-bit addition. Therefore, the required area is reduced significantly without any reduction in speed
Keywords :
digital arithmetic; dividing circuits; chip area reduction; division algorithm; two´s complement high radix division; Costs;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN :
0-7803-3583-X
Type :
conf
DOI :
10.1109/ISCAS.1997.621568
Filename :
621568
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=315724
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