• DocumentCode
    315727
  • Title

    Mixed signal design of cascadable matched filters

  • Author

    Su, Chauchin ; Lin, Hung-Chi ; Jou, Shye-Jye

  • Author_Institution
    Dept. of Electr. Eng., Nat. Central Univ., Chung-Li, Taiwan
  • Volume
    3
  • fYear
    1997
  • fDate
    9-12 Jun 1997
  • Firstpage
    2108
  • Abstract
    This paper presents the design, implementation, and test of a mixed signal matched filter. It uses simple current mirrors to reduce the complexity of the crucial summation circuit. The circuit is small in size and regular in structure. They can be cascaded into filters of longer length. A 128-chip test chip has been implemented in a 2.5 mm2 core by 0.8 μm SPDM digital CMOS technology. The DC and AC measurement assert the feasibility of the design
  • Keywords
    CMOS integrated circuits; cascade networks; integrated circuit design; matched filters; mixed analogue-digital integrated circuits; 0.8 micron; CMOS technology; cascadable matched filters; current mirrors; mixed signal design; summation circuit; Adders; Automatic control; CMOS technology; Circuits; Correlators; Delay lines; Digital filters; Matched filters; Mirrors; Signal design;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
  • Print_ISBN
    0-7803-3583-X
  • Type

    conf

  • DOI
    10.1109/ISCAS.1997.621573
  • Filename
    621573
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=315727