Title :
Impact of CMOS device scaling in ASICs on radiation immunity
Author :
Ragaie, H. ; Kayed, S.
Author_Institution :
Electron. & Comm. Eng. Dept., Ain Shams Univ., Cairo, Egypt
Abstract :
Roadmaps for CMOS device technology has shown fast pace scaling in recent years. Mainstream CMOS devices have been produced with feature sizes between 0.1 and 0.25 μm since the year 2000 and the so called "fundamental limit" will be reached around the year 2014. This paper reviews the effects of radiation on deep submicron CMOS devices and techniques to harden ASICs against these effects for applications in the space environment, emphasizing the impact of device scaling according to the ITRS roadmap. Radiation effects include traditional ones, such as total ionization dose effects, single-event upset and latchup, as well as newer effects such as hard-errors induced by heavy ions microdoses, gate-rupture and ion-triggered channeling.
Keywords :
CMOS integrated circuits; application specific integrated circuits; integrated circuit design; integrated circuit reliability; radiation effects; radiation hardening (electronics); space vehicle electronics; 0.1 to 0.25 micron; ASIC radiation immunity; CMOS device feature sizes; CMOS device scaling; deep submicron CMOS device radiation effects; gate-rupture; heavy ions microdose hard-errors; ion-triggered channeling; latchup; radiation hardening; single-event upset; total ionization dose effects; CMOS technology; Ionization; Radiation effects; Radiation hardening;
Conference_Titel :
Electronic Devices, 2002. (EWAED). The First Egyptian Workshop on Advancements of
Print_ISBN :
977-5031-73-7
DOI :
10.1109/EWAED.2002.1177875
