iiQueue, a QoS-oriented queue module for input-buffered ATM switches

Author

Kang, S.M. ; Duan, H. ; Lockwood, J.W. ; Will, J.D.

Author_Institution

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

Volume

3

fYear

1997

fDate

9-12 Jun 1997

Firstpage

2144

Abstract

This paper discusses the principle of a versatile, 3-dimensional queue (3DQ) and its prototype implementation-illinois input Queue (iiQueue) module for input-buffered ATM switches. 3DQ uses pointers and linked lists to organize ATM cells into multiple virtual queues according to priority, destination, and virtual connection. It enforces per virtual connection Quality-of-Service (QoS) and avoids Head-Of-Line (HOL) blocking. Implemented with field programmable gate array (FPGA) devices for the core 3DQ logic on a 6-layer printed circuit board (PCB), iiQueue prototype module can process ATM cells at 622 Mb/s (OC-12). With multichip module (MCM) and fast GaAs logic implementation, iiQueue module is expected to process cells at 2.5 Gb/s (OC-48)

Keywords

asynchronous transfer mode; broadband networks; field programmable gate arrays; telecommunication switching; 2.5 Gbit/s; 622 Mbit/s; FPGA devices; QoS-oriented queue module; core 3DQ logic; fast logic implementation; iiQueue; implementation-illinois input Queue; input-buffered ATM switches; linked lists; multichip module; multiple virtual queues; three-dimensional queue; virtual connection; Asynchronous transfer mode; Field programmable gate arrays; Logic circuits; Logic devices; Printed circuits; Programmable logic arrays; Prototypes; Quality of service; Switches; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on

Print_ISBN

0-7803-3583-X

Type

conf

DOI

10.1109/ISCAS.1997.621594

Filename

621594