Design and analysis of a new microthyristor based SRAM cell

Author

Zekry, A. ; Hafez, I.M. ; El-Hady, M.

Author_Institution

Electron. & Commun. Eng. Dept., Ain Shams Univ., Cairo, Egypt

fYear

2002

fDate

28 Sept. 2002

Firstpage

70

Lastpage

84

Abstract

This work introduces three new SRAM cell configurations based on a microthyristor as a binary storage element. We designed these cells and outlined their fabrication process. Their performance has been simulated using the PSPICE circuit simulator. It was found that the delay time is about one nanosecond, the power dissipation amounts to 0.8 μW for the logic one and the cell size is about 10 μm². These characteristics outperform the classical CMOS SRAM cell implemented with the same minimum feature size of 2λ=0.38 μm. Introducing these SRAM cells a new development phase for SRAM cells could be started having impact on advanced logic systems.

Keywords

SPICE; SRAM chips; circuit simulation; integrated circuit design; integrated circuit modelling; logic design; logic simulation; thyristor circuits; thyristors; 0.38 micron; 0.8 muW; CMOS SRAM; PSPICE; SRAM cell configurations; cell delay time; cell power dissipation; microthyristor based SRAM cells; microthyristor binary storage elements; minimum feature size; thyristors; CMOS logic circuits; Circuit simulation; Delay effects; Fabrication; Power dissipation; Random access memory; SPICE;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Devices, 2002. (EWAED). The First Egyptian Workshop on Advancements of

Print_ISBN

977-5031-73-7

Type

conf

DOI

10.1109/EWAED.2002.1177879

Filename

1177879