A low power 8T SRAM cell design technique for CNFET

In this paper, a new SRAM cell design based on carbon nanotube field-effect transistor (CNFET) technology is proposed. Carbon nanotube with their superior transport properties, excellent thermal conductivities, and high current handling capacities has proved to be a promising alternative device to the conventional CMOS. The proposed SRAM cell design on CNFET is compared with SRAM cell designs implemented with the conventional CMOS and FinFET in terms of speed, power consumption, stability, and leakage current in this paper. The HSPICE simulation and analysis show that the dynamic power consumption of the proposed 8T CNFET SRAM cell´s is reduced about 48% and the SNM is widened up to 56% compared to the conventional 6T CMOS SRAM structure at the expense of 2% leakage power and 3% write delay increase.