Full-precision bidirectional bit-serial convolver for real-time image processing

A novel chip implementing real-time image convolution features a pure bit-serial architecture and systolic array structure. It consists of a 3×3 array of modular units that can be easily enlarged. The basic unit heart is a very efficient bidirectional multiplier, which can perform two different multiplications simultaneously. The chip overall size is 5.78 mm × 3.18 mm (in CMOS 2μ technology). It is full-precision and has a throughput of one 20 bit convolution every 10 clock cycles, with a latency of 24 clock cycles