Frequency Generation for Mobile RFID Reader

This paper presents a 0.18-mum CMOS fully integrated LC VCO and fractional-N phase-locked loop(PLL), suitable for radio frequency identification (RFID) reader working at 900 MHz. The VCO comprises cross-coupled double core and PMOS tail current source to suppress 1/f noise up conversion. To minimize pulling, the 900 MHz VCO is generated by a 1.8 GHz VCO followed by a frequency divider. In addition, current source of this topology was applied bandgap reference to reduce effect of temperature and supply voltage variation, which is caused by unstable oscillation state. The phase noise of a free-running VCO is demonstrated with -106 dBc/Hz at 100kHz offset. The PLL´s loop bandwidth is measured to be 64KHz, with a fractional spurious level of -83dBc. The power consumption of the VCO including bandgap reference, frequency divider, and buffer amplifiers is 39.5mW and the PLL is 21.6mW from a 1.8V supply voltage