Future trends in microprocessors: out-of-order execution, speculative branching and their CISC performance potential

Current microprocessors with one execution core are already reaching the performance limit of close to one Instruction Per Cycle. Thus, in order to comply with the existing market demands of a ^~ 1.5X performance improvement each year, new ideas and techniques are needed for designing future microprocessors Running instructions out of order, in parallel on multiple execution units, coupled with techniques for resolving dependencies between instructions (data or control flow), can provide the performance improvement expected, utilizing more fine grain parallelism. This paper surveys some of these ideas and techniques, and presents a conceptual CISC Superscalar microprocessor model incorporating them. Its performance potential is evaluated via a trace driven software simulator