DocumentCode
3158328
Title
BIDIC, a CMOS implementation of a bipolar digital correlator
Author
Baker, K.F., Jr. ; Horner, J.G.
Author_Institution
Dept. of Electr. Eng., Tennessee Univ., Knoxville, TN, USA
fYear
1990
fDate
1-4 Apr 1990
Firstpage
272
Abstract
An architecture useful in bipolar digital correlation is shown and explained. A chip which performs binary correlation on an 8-bit sampled data stream is described. The chip is a proof-of-concept chip in that it only contains 32 stages of sampled data. The chip has been fabricated in 2-μm CMOS using the MOSIS fabrication service. It is expected that the maximum clock rate of the chips will be 1.7 MHz. Work concerning the architecture and the implementation is described. An ASIC implementation of the system is given
Keywords
CMOS integrated circuits; application specific integrated circuits; correlators; digital integrated circuits; 1.7 MHz; 2 micron; 2-μm CMOS; 8 bit; ASIC; BIDIC; MOSIS fabrication service; binary correlation; bipolar digital correlation; bipolar digital correlator; chip architecture; clock rate; proof-of-concept chip; sampled data stream; Application specific integrated circuits; Correlators; Energy resolution; Matched filters; Multiplexing; Pulse compression methods; Shift registers; Signal resolution; Ultrasonic imaging; Ultrasonic variables measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Southeastcon '90. Proceedings., IEEE
Conference_Location
New Orleans, LA
Type
conf
DOI
10.1109/SECON.1990.117815
Filename
117815
Link To Document