Design and implementation of 16-bit fixed point digital signal processor

This paper deals with the design and implementation of the 16-bit fixed point digital signal processor. The designed DSP has 211 instructions and consists of 40-bit ALU, 6 level pipelines, 17-bit X 17-bit parallel multiplier for single-cycle MAC operation, 8 addressing modes, 8 auxiliary registers, 2 auxiliary register arithmetic units, two 40-bit accumulators and 2 address generators. The verilog HDL coded synthesizable RTL code of the DSP core has a complexity of 69,860 in the two input NAND gates. We verified the functions of the DSP by a simulation with a single instruction test as the first step. and then implemented the DSP with the FPGA. The test vectors have a single instruction test, combination of single instructions and algorithm applications, ADPCM vocoder and the MP3 decoder. After FPGA verification, the DSP core is fabricated with 0.25 um CMOS technology. The DSP core carried out three test vector sets which are tested at FPGA at the 106 MHz clock rates.