Title :
Implementation of 3D graphics accelerator using full pipeline scheme on FPGA
Author :
Kim, Kyungsu ; Hoosung-Lee ; Cho, Seonghyun ; Park, Seongmo
Author_Institution :
SoC Res. Dept., Electron. & Telecommun. Res. Inst., Daejeon
Abstract :
This paper proposes effective 3D graphics hardware. It is designed to support the OpenGL ES 2.0 and Shader model 3.0. We develop all module (vertex shader, clipping engine, triangle setup engine, rasterizer, pixel shader and raster operator) of 3D pipeline on FPGA using RTL design. The proposed hardware of which total gate count is about 1.486 M operates with 100 Mpixels/sec at pixel shader. Compared to the other product of a company, the proposed architecture result in about 50% improvement in term of cycle.
Keywords :
computer graphics; field programmable gate arrays; graphical user interfaces; pipeline processing; 3D graphics accelerator; 3D pipeline; FPGA; OpenGL ES 2.0; RTL design; Shader model 3.0; clipping engine; pixel shader; raster operator; rasterizer; shader; triangle setup engine; vertex; Field programmable gate arrays; Graphics; Pipelines; 3D Graphics; 3D pipeline; FPGA; pixel shader; vertex shader;
Conference_Titel :
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location :
Busan
Print_ISBN :
978-1-4244-2598-3
Electronic_ISBN :
978-1-4244-2599-0
DOI :
10.1109/SOCDC.2008.4815693
