10-bit charge redistributed D/A Converter for TFT-LCD driver

In this paper, a 10-bit charge redistributed CMOS D/A Converter is presented for LCD panel driving. The structure of the charge redistributed D/A Converter is consisted of OP-AMP as Unit Gain Sampler, two parallel capacitors, a CMOS switch, and a digital block. In order to solve the capacitor mismatching problem, a compensation method to use alternate capacitors is proposed. Further, the D/A Converter has a digital block to change the digital parallel data into the serial data, which is based on JCCG (Johnson Counter Clock Generator). The chip was fabricated with a 0.35 mum 1-poly 4-metal n-well CMOS technology. The effective chip area is 430 mum times 880 mum and it dissipates about 0.607 mW power consumption at 3.3V power supply. The INL and DNL is within plusmn0.41 LSB and plusmn0.11 LSB, respectively.