Design of 24 bit DSP for audio algorithms

This paper describes the architecture and design procedure of a DSP (Digital Signal Processor) for the digital audio applications. The suggested DSP has fixed 24 bit data structure, 6 stage pipeline, and 125 instructions. Some of the instructions are specially designed for the audio signal processing. Almost instructions are completed within a single cycle. The designed DSP has been verified by comparing the results from CBS (Cycle based Simulator) and those of HDL simulation through the single instruction set test, the instruction combination test, and real audio applications. Finally, we confirm by the HDL simulation that the DSP carried out successfully out ADPCM and MPEG-2 AAC decoding algorithm. The DSP core is implemented in 0.18 mum CMOS process and operates at 120 MHz.