DocumentCode
3159667
Title
Design & verification of 16 bit RISC processor
Author
Jung, Seung Pyo ; Xu, Jingzhe ; Lee, Donghoon ; Park, Ju Sung ; Kim, Kang-joo ; Cho, Koon-shik
Author_Institution
Sch. of Electron. & Electr. Eng., Pusan Nat. Univ., Busan
Volume
03
fYear
2008
fDate
24-25 Nov. 2008
Abstract
The procedure of design and verification for a 16-bit RISC processor is introduced in this paper. The proposed processor has Harvard architecture and consists of 24-bit address, 5-stage pipeline instruction execution, and internal debug logic. ADPCM vocoder and SOLA algorithm are successfully carried out on the processor made with FPGA.
Keywords
field programmable gate arrays; formal verification; logic design; microprocessor chips; pipeline processing; reduced instruction set computing; 5-stage pipeline instruction execution; ADPCM vocoder; FPGA; Harvard architecture; RISC processor design; RISC processor verification; SOLA algorithm; internal debug logic; Application specific integrated circuits; Debugging; Logic; Personal digital assistants; Pipelines; Portable media players; Program processors; Reduced instruction set computing; Registers; Repeaters; 16bit RISC Processor Harvard architecutre; 5 stage pipeline; Block Repeater; Multiplier;
fLanguage
English
Publisher
ieee
Conference_Titel
SoC Design Conference, 2008. ISOCC '08. International
Conference_Location
Busan
Print_ISBN
978-1-4244-2598-3
Electronic_ISBN
978-1-4244-2599-0
Type
conf
DOI
10.1109/SOCDC.2008.4815726
Filename
4815726
Link To Document