Title :
Rapid-prototyping of high-performance RISC cores with VHDL
Author :
Bautista, TomÁs ; Marrero, Gustavo ; Carballo, Pedro P. ; Nunez, Antonio
Author_Institution :
CAD Div., Univ. of Las Palmas de Gran Canaria, Spain
Abstract :
The authors present some experiences they have obtained in the conception and description of a SPARC v8 IU core to be embedded in custom applications. Its design has been carried out using VHDL-based tools such as Synopsys for debugging and synthesis, and Cascade´s Epoch for the final implementation stage. These experiences have been gathered into a proposed methodology for the rapid design of high-performance embeddable cores
Keywords :
computer debugging; hardware description languages; reduced instruction set computing; Cascade Epoch; SPARC v8 IU core; Synopsys; VHDL; VHDL-based tools; debugging; high-performance RISC cores; high-performance embeddable cores; rapid design; rapid prototyping; synthesis; Analog circuits; Debugging; Design automation; Design methodology; Electronic design automation and methodology; Hardware design languages; Libraries; Manufacturing; Microelectronics; Reduced instruction set computing;
Conference_Titel :
VHDL International Users' Forum, 1997. Proceedings
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-8180-2
DOI :
10.1109/VIUF.1997.623928
