Title :
Extraction of token based VHDL models from old ASIC net lists
Author :
Söderberg, Dennis
Author_Institution :
Electron. Lab., Defence Mater. Adm., Linkoping, Sweden
Abstract :
The author discusses the understanding of old ASIC components by extraction of VHDL models. To support the extraction process he has developed a pattern matching routine that can use both measured data or data from simulations. As he does not have access to tools that support automatic symbolic extraction, many processes had to be performed manually
Keywords :
application specific integrated circuits; field programmable gate arrays; hardware description languages; logic CAD; pattern matching; ASIC net lists; FPGA; application specific integrated circuits; automatic symbolic extraction; field programmable gate arrays; measured data; pattern matching routine; simulation data; token based VHDL model extraction; Application specific integrated circuits; Automata; Data mining; Documentation; Integrated circuit technology; Intellectual property; Laboratories; Pattern matching; Petri nets; Software libraries;
Conference_Titel :
VHDL International Users' Forum, 1997. Proceedings
Conference_Location :
Arlington, VA
Print_ISBN :
0-8186-8180-2
DOI :
10.1109/VIUF.1997.623945
