Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations

This paper presents coarse-grained reconfigurable architecture supporting floating-point operations, where each integer processing element is paired with its neighbor to perform floating point operations. One processing element in a pair is in charge of the mantissa part, and the other is in charge of the exponent part. With an 8 times 2 array of processing elements, 8 floating-point operations can be performed at the same time. The chip is fabricated in MagnaChip/Hynix 0.18 mum technology with the gate count of 363,013 and clock frequency of 116.8 MHz in the typical case.