High performance on-chip-network architecture with multiple channels and dual routing

We design and implement an high performance on-chip-network, which is composed of Soc network architecture (SNA) and eXtended SoC Network Protocol (XSNP). The SNA is a hardware architecture for on-chip-buses, which provide simultaneous multiple channels and dual routing. The XSNP is an interface protocol for the SNA which provides compatibility with the AHB protocol. The SNA system is adequate for parallel processing systems with multiple processors. FIR filter systems are designed to verify the performance of the on-chip-bus using 1-, 2-layer AHB and the SNA. The performance is compared using simulation and implementing using FPGAs.