SoC platform design with multi-channel bus architecture

Author

Jung, Younjin ; Kim, Ok ; Lee, Byoungyup ; Hongkyun Jung ; Ryoo, Kwangki

Author_Institution

Grad. Sch. of Inf. & Commun., Hanbat Nat. Univ., Daejeon

Volume

03

fYear

2008

fDate

24-25 Nov. 2008

Abstract

We have designed an SoC platform with a multi-channel bus architecture which can reduce the bottleneck of on-chip communication by multi-channels. The platform consists of OpenRISC 1200 processor, WISHBONE crossbar on-chip bus, memory interface, VGA controller, DMA, AC97 controller, debug interface and UART. The crossbar on-chip bus supports up to 8 masters and 16 slaves, WISHBONE compatible peripheral IPs and allows more than one master to use the bus because of multiple channels. The proposed platform is implemented on Altera´s EP2C70F672 FPGA device. As a result of the test program, the proposed platform has better efficiency by 26.58% than the SoC platform with shared bus on-chip bus.

Keywords

data communication equipment; field buses; field programmable gate arrays; integrated circuit design; microprocessor chips; system-on-chip; AC97 controller; Altera EP2C70F672 FPGA device; DMA; OpenRISC 1200 processor; SoC platform design; UART; VGA controller; WISHBONE crossbar on-chip bus; debug interface; memory interface; multichannel bus architecture; Communication channels; Communication system control; Data communication; Field programmable gate arrays; Master-slave; Random access memory; Reduced instruction set computing; Registers; Testing; Video sharing; SoC platform; multi-channel on-chip bus;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference, 2008. ISOCC '08. International

Conference_Location

Busan

Print_ISBN

978-1-4244-2598-3

Electronic_ISBN

978-1-4244-2599-0

Type

conf

DOI

10.1109/SOCDC.2008.4815743

Filename

4815743