Cu via Exposure by Backgrinding for TSV Applications

Microelectronics packaging is driven by the continuous increase in demands for smaller, faster and cheaper products. A 3D package with Silicon carrier is developed in this work. The Silicon carrier technology has added advantages such as higher thermal conductivity, no CTE mismatch between the chip and substrate, high density interconnection etc. A key technology in silicon carrier is TSV process. We developed TSV process using via first approach in this work. The electroplated copper via is polished using chemical mechanical polishing and the burrier via is exposed by mechanical backgrinding. In this paper, copper polishing process details, via exposure technique have been presented. The silicon wafer surface after via exposure has been analyzed and found no copper smudging.