DocumentCode
3160627
Title
Dynamically reconfiguration of PLL using FPGA
Author
Bhambore, Archana S. ; Harkare, R.R.
Author_Institution
Dept. of Electron. (VLSI), Shri. Ramdeobaba Kamla Nehru Eng. Coll., Nagpur, India
fYear
2010
fDate
17-19 Sept. 2010
Firstpage
260
Lastpage
264
Abstract
This paper generally relates to phase locked loops and more particularly to reconfiguration of phase locked loops used for signal synchronization on integrated circuit chips. A circuit to dynamically reconfigure the clock frequency of a synchronous digital system according to the changing needs of the application is described in this paper. The circuit changes the clock frequency with a minimal time penalty and offers glitch free, reliable operation.
Keywords
clocks; field programmable gate arrays; phase locked loops; synchronisation; FPGA; PLL; clock frequency; integrated circuit chips; phase locked loops; signal synchronization; synchronous digital system; Clocks; Cyclones; Field programmable gate arrays; Phase locked loops; Radiation detectors; Synchronization; Time frequency analysis; PLL Reconfiguration; Run-Time Reconfiguration; clock distribution network;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer and Communication Technology (ICCCT), 2010 International Conference on
Conference_Location
Allahabad, Uttar Pradesh
Print_ISBN
978-1-4244-9033-2
Type
conf
DOI
10.1109/ICCCT.2010.5640519
Filename
5640519
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