High performance CMOS circuit techniques for the G-4 S/390 microprocessor

Author

Warnock, J. ; Sigal, L. ; Curran, B. ; Chan, Y.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

1997

fDate

12-15 Oct 1997

Firstpage

247

Lastpage

252

Abstract

This paper describes the CMOS circuit techniques used in the design of the high performance Generation-4 S/390 microprocessor. Successful system operation at frequencies up to 400 MHz was achieved through careful static circuit design and timing optimization, along with the limited use of dynamic circuits for highly critical functions, and several different clocking/latching strategies for cycle time reduction. A variety of innovative full-custom circuit techniques were used in the dataflow design. Timing-driven synthesis of the control logic provided maximum flexibility with minimum turn-around time, while still matching the performance level set by the custom parts of the design. The on-chip LI cache was designed extensively with self-resetting CMOS (SRCMOS) circuitry to provide a 2.0 ns access time and up to 500 MHz operation

Keywords

CMOS digital integrated circuits; microprocessor chips; network synthesis; CMOS circuit techniques; G-4 S/390; Generation-4 S/390 microprocessor; dataflow design; dynamic circuits; highly critical functions; on-chip LI cache; self-resetting CMOS; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Design optimization; Frequency; Level set; Logic design; Microprocessors; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628875

Filename

628875