Low power design of an SRAM cell for portable devices

This paper focuses on the power dissipation during the Write operation in CMOS SRAM cell for different frequencies. Charging and Discharging of Bit Lines consume more power during the Write “1” and Write “0” operation. In this paper a Proposed SRAM cell, includes two more trail Transistors in the pull down path for proper charging and discharging of Bit Lines. The Proposed SRAM cell designed and implemented with using 90 nm CMOS technology. The Proposed SRAM has been designed and simulated by Microwind 3.1 software. The results of Proposed SRAM cell are taken on different frequencies at power supply of 1V. Finally the results are compared with Conventional 6T SRAM cell. The power dissipated in Proposed SRAM cell reduced by 12-38% in comparison to Conventional SRAM cell.