Lithography for Patterning inside through-Si Vias

Lithographic patterning inside through Si vias (TSV) requires conformal coating of resist over high topography and exposure with a large gap distance. This paper investigates some parameters that have an effect on the resist pattern definition at the bottom of ~100 mum deep via. The influences of the large gap exposure, resist thickness and resist type to the dimension of resist patterns have been studied. The relation of resist thickness to the size of the Si vias is also reported. Finally, an example of patterned resist inside via as a masking layer for dielectric patterning is presented as well.