DocumentCode
3161219
Title
High-speed FPGA implementation of an improved LMS algorithm
Author
Xianglei Dong ; Huiyong Li ; Yu Wang
Author_Institution
Sch. of Electron. Eng., Univ. of Electron. Sci. & Technol. of China, Chengdu, China
fYear
2013
fDate
26-28 Oct. 2013
Firstpage
342
Lastpage
345
Abstract
The FPGA implementation of a new parallel processing method is studied by introducing the parallel processing method into the delayed least mean square (DLMS) algorithm. The parallel delayed least mean square (PDLMS) algorithm has the faster data throughput and higher convergence rate than the DLMS algorithm. In this paper, the hardware implementation of PDLMS is realized by hardware description language, while the simulation structure is presented. The results show that the PDLMS algorithm has certain superiority according to DLMS.
Keywords
field programmable gate arrays; hardware description languages; least mean squares methods; parallel processing; FPGA implementation; PDLMS algorithm; hardware description language; parallel delayed least mean square algorithm; parallel processing method; Adaptive filters; Algorithm design and analysis; Clocks; Convergence; Field programmable gate arrays; Least squares approximations; Signal processing algorithms; FPGA; PDLMS; adaptive filtering; parallel processing;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Problem-solving (ICCP), 2013 International Conference on
Conference_Location
Jiuzhai
Type
conf
DOI
10.1109/ICCPS.2013.6893535
Filename
6893535
Link To Document