DocumentCode
3161705
Title
Reliability Aspects of Microinsert Based Interconnection Technologies
Author
Mathewson, A. ; Brun, J. ; Franiatte, R. ; Nowodzinski, A. ; Sillon, N. ; Depoutot, F. ; Dubois-Bonvalot, B.
Author_Institution
CEA, Grenoble
fYear
2007
fDate
10-12 Dec. 2007
Firstpage
227
Lastpage
232
Abstract
Face to face interconnection is an important technology for the assembly of heterogeneously integrated systems, it permits the integration of technologies from disparate backgrounds and allows separate technology optimization prior to assembly. This paper reports work on the optimization of micro-insert technology, which allows the electrical connection between the two systems. Thermal cycling of wafers between -40degC and + 85degC has been performed at wafer level and results indicate that the average resistance of the daisy chain observed between the two devices does not change significantly. However, the standard deviation of the distribution increases slightly as a consequence of thermal cycling. Analysis of interconnect and contact resistance indicates that while metal interconnect resistance diminishes, possibly as a function of annealing effects and grain growth. The resistance of individual contacts between devices is increasing somewhat. These two phenomena are considered to be effectively canceling each other out to provide the macroscopic behavior reported above. An average contact resistance of 14 mOmega was observed in devices which had undergone almost 500 cycles (an increase of ~6 mOmega from the starting resistance.
Keywords
annealing; contact resistance; integrated circuit interconnections; thermal management (packaging); wafer bonding; wafer level packaging; annealing effects; chip to chip interconnection; contact resistance; electrical connection; grain growth; heterogeneously integrated system assembly; metal interconnect resistance; microinsert based interconnection technologies; standard deviation; temperature -40 C to 85 C; thermal cycling; thermal management; wafer bonding; Assembly systems; Contact resistance; Hardware; Integrated circuit interconnections; Packaging; Substrates; Surface topography; Testing; Thermal management; Thermal resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronics Packaging Technology Conference, 2007. EPTC 2007. 9th
Conference_Location
Singapore
Print_ISBN
978-1-4244-1323-2
Electronic_ISBN
978-1-4244-1323-2
Type
conf
DOI
10.1109/EPTC.2007.4469776
Filename
4469776
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