TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model

Author

Takamura, Akihiro ; Kuwako, Masashi ; Imai, Masashi ; Fujii, Taro ; Ozawa, Motokazu ; Fukasaku, Izumi ; Ueno, Yoichiro ; Nanya, Takashi

Author_Institution

Graduate Sch. of Inf. Sci. & Eng., Tokyo Inst. of Technol., Japan

fYear

1997

fDate

12-15 Oct 1997

Firstpage

288

Lastpage

294

Abstract

Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3 MIPS using the Dhrystone V2.1 benchmark

Keywords

asynchronous circuits; microprocessor chips; 32 bit; 32-bit asynchronous microprocessor; 32-bit microprocessor; 52.3 MIPS; Dhrystone V2.1; TITAC-2; asynchronous VLSI; asynchronous design; clock skew; scalable-delay-insensitive; scalable-delay-insensitive model; CMOS technology; Circuits; Clocks; Delay effects; Delay systems; Information science; Microprocessors; Very large scale integration; Wire; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design: VLSI in Computers and Processors, 1997. ICCD '97. Proceedings., 1997 IEEE International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-8186-8206-X

Type

conf

DOI

10.1109/ICCD.1997.628881

Filename

628881