DocumentCode
3161767
Title
Modelling of synchronous sequential machines with time-delayed Petri nets
Author
Moldoveanu, Florin ; Cernat, Mihai ; Comnac, Vasile ; FLOROIAN, Dan
Author_Institution
Fac. of Electr. Eng. & Comput. Sci., Brasov Univ., Romania
fYear
2002
fDate
1 Dec. 2002
Firstpage
240
Abstract
The use of a Petri net for a sequential control model in designing state machines (sequential machines) has proved important, and is known as a control technique interpreted Petri net (SIN). This paper describes hardware realization of a SIN as a synchronous sequential scheme. It considers realization of the structural elements of the SIN net, synchronous sequential realization of net structures, test oriented arcs and synchronous marking memories.
Keywords
Petri nets; sequential circuits; sequential machines; SIN net; control technique interpreted Petri net; hardware realization; net structures; sequential control model; state machines; structural elements; synchronous marking memories; synchronous sequential machines; test oriented arcs; time-delayed Petri nets; Automata; Automatic control; Computer science; Hardware; Input variables; Petri nets; Random access memory; Sequential circuits; Signal processing; Silicon compounds;
fLanguage
English
Publisher
ieee
Conference_Titel
Electrical and Electronics Engineers in Israel, 2002. The 22nd Convention of
Print_ISBN
0-7803-7693-5
Type
conf
DOI
10.1109/EEEI.2002.1178424
Filename
1178424
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