High-speed structure of channel estimation and equalization for 60 GHz SC-FDE transmission

In this paper, we design high-throughput structures of channel estimation and equalization modules for 60 GHz SC-FDE transmission based on the IEEE 802.11ad standard. In the implementations of high speed transmission, inter-symbol interference (ISI) is significant, which severely degrades the biterror-rate (BER) performance. So channel estimation and equalization are particularly important in receiver. In the channel-estimation module, efficient Golay correlator (EGC) that has low complexity is exploited. Radix-2² fast-Fourier-transform (FFT) algorithm and pipeline-processing method are adopted in the equalization module. The divider used in the calculation of equalizer coefficient is designed with lookup table (LUT). At last, the 8-parallel high-speed structure has been implemented on a Xilinx Virtex-6 FPGA device, where the maximum throughput of channel-estimation and equalization modules can be up to 1.76 Gbps and 1.44 Gbps, respectively.