A parallel system for test pattern generation

The problem of generating test pattern sequences for digital circuits is a crucial one in the area of electronic CAD. While a significant effort has been made to develop new and more powerful algorithms to solve it, the required CPU times are still unacceptable in many cases. The authors propose a different approach based on the use of a general-purpose parallel architecture. The attention is devoted to combinational circuits described at the gate level, and faults are modeled as permanent single stuck-ats. Parallelization strategies are discussed, together with an implementation on a transputer-based machine. The resulting system significantly speeds-up the test generation process: its performance is discussed, also reporting the experimental results obtained on the standard set of bench-mark combinational circuits