Digital Receiver Design Using VHDL Generation From Data Flow Graphs

This paper describes a design methodology, a library of reusable VHDL descriptions and a VHDL generation tool used in the application area of digital signal processing, particularly digital receivers for communication links. The tool and the library interact with commercial system simulation and logic synthesis tools. The support of joint optimization of algorithm and architecture as well as the concept for design reuse are explained. The algorithms for generating VHDL code according to different user specifications are described. An application example is used to show the benefits and current limitations of the proposed methodology.