Design-Flow and Synthesis for ASICs: A Case Study

The growing complexity of devices to be designed and manufactured, and the need to reduce the time-to-market, stress the importance of sound design methodologies. In this framework formal synthesis has the advantage of increasing the quality both of the design process and of the realized devices. The problem of relating the different abstraction levels involved in the extended design process is solved through the use of logic synthesis tools. The evaluation of the design constraints, characterizing optimal implementations such as area and timing, provide the most pragmatic approach to identify efficient guidelines applicable in the abstract phases of the design flow. The resulting design methodology combining both formal and more traditional design tools has been tested on a complex device in the area of telecommunications.